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Hi All, I have written code to add a net expression to all the global signals in a cell, however, it does not make change to the signal's net name. The command I am using is: dbReplaceSigExpr( cv netexpr ) it only add a property name and default name to the net. I am wondering is there any command that I could use to make changes to an existing net name?
Thanks, Min. 2. I'm using ADE L to perform a simulation on a circuit (if you've read my previous posts the circuiti is called Pixel:P). The problem is with the clock signal: the rising time and the falling time that I can see in the generated graph at the end of the simulation are set to 3ns and 2ns respectively.
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Instead, I want to set these values to 10ps. (the clock is generated in the TB using a simple Always statement in the verilog code). To do this I'm following this procedure: open Virtuoso, select Tool - CDF - Edit, select the library where I have to circuit (Francesco1), select two components called MOSa2d and MOSd2a and change the values to 10ps. The problem is, even if I do this procedure, the result doesn't change.
I don't know if these are enough informations to understand the problem, because I first don't really have a clear comprehension of what is going on when I make this change in the library. Thanks in advance! Hi all, I am writing a script to add net expressions to all the global signals in a schematic for all the cells in a library. At the current stage, my function is able to make change in one cell. However, I could not find a good way to go through every cell in the library.
Is typing out all the cell names the only way to form the list? Or there is some other ways, that allow me to go through the whole list of cells in the library? Thanks, Min. 4. What's the best and what's the easiest way to convert a struct to an association list? Say I have a structure named s.
I can access the property list with s- ??, which returns a list containing (name1 value1 name2 value2. However I need an association list: ((name1 value1) (name2 value2).) I thought a function exist to perform this basic (i.e. Converting from data-structures), but couldn't find anything in the documentation.
Thanks for any hint! Similar Threads: 1. Hi, I have a VHDL model where a number of nodes are talking to each other as well as a register file, using a common pair of address-data buses with requests and acks for arbitration. Each node has a single process with an FSM that governs its working.
The model works correctly in ModelSim, but I face problems when synthesising. I am using the Xilinx ISE version 6.1i for this. The synthesis phase completes, but XST throws a lot of warnings like the one below: WARNING:Xst:638 - in unit topentity Conflict on KEEP property on signal rfileinstMtridatadatabus and node2instMtridatadatabus node2instMtridatadatabus signal will be lost. 'node2inst' is an instance of a component called 'node2' in an entity called 'topentity'. 'databus' is an inout stdlogicvector port on the node2 entity. I had searched the newsgroups for similar problems and learned about the 'equivalentregisterremoval' and 'keep' attributes.
But the signal mentioned here, 'Mtridatadatabus' is inferred internally by the synthesiser, so I have no idea how to set these attributes on this signal! Setting this attribute for just 'databus' doesn't seem to help. Inspite of these warnings, the synthesis phase finishes, but the 'translate' phase aborts after this error from NGDBUILD: ERROR:NgdBuild:456 - logical net 'rfileinstMtridatadatabus' has both active and tristate drivers I have no idea how to rectify this error.
And this seems to occur only for the Virtex and Spartan FPGAs. I tried synthesising for the CoolRunner CPLD, and everything worked out without any error. How do I address this from my VHDL code? Or is this a tool or platform specific problem? MENTORGRAPHICSLEONARDOSPECTRUMV2003B, MODELSIMSEPLUSV5.7F, NATIONALINSTRUMENTSDIGITALWAVEFORMEDITORV1.0, CSTDESIGNSTUDIOV2.3, SYNOPSYSFPGACOMPILERIIV3.8, SYNOPSYSSTAR-HSPICEV2003.09, XILINXCHIPSCOPEPROV6.2i, XILINXSYSTEMGENERATORV3.1, - new! CSTDESIGNSTUDIOV2.3, CSTEMSTUDIOV1.3 MENTORGRAPHICSLEONARDOSPECTRUMV2003B MODELSIMSEPLUSV5.7F NATIONALINSTRUMENTSDIGITALWAVEFORMEDITORV1.0 SYNOPSYSFPGACOMPILERIIV3.8 SYNOPSYSFPGACOMPILERIIV3.8SOLARIS SYNOPSYSSTAR-HSPICEV2003.09LINUX SYNOPSYSSTAR-HSPICEV2003.09 XILINXCHIPSCOPEPROV6.2i XILINXSYSTEMGENERATORV3.1 for more info please send email 3. Hi, How to determine the exact minimum clock period of a particular design using Xilinx ise (6.2i) tool, or other tools if possible?
After Placement & route (PAR) Simulation results should come inside that Minimum clock period (MCP)? I m asking this question because, xilinx ise (6.2i) is giving me 12.766 ns of min. Clock period in PAR report and i m getting my proper output after PAR, if i m keeping MCP of design 20 ns? So it is required by me to investigate proper mechanism to find out the MCP of any design????? Pls Help me out.
Pls reply asap. Hi Friends Friends, i have been struggling for 1.5 months on a problem.Let me explain u a little bit. I am working on FPGA implementation of Dijkstra's Shortest Path Algorithm on XILINX 7.1 ISE.Now I hav implemented the code in verilog.The Number of nodes in my case is 256(IF U REQUIRE MY CODE I WILL SEND IT).The tragedy is that the code is working fine but when i m synthesizing it it is giving the following error which i am unable to resolve. The error is ' Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 1869512 kb. Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy the problem, first: Try increasing your system's RAM.
Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix the problem, please try the following: Search the Answers Database at support.xilinx.com to locate information on this error message.
If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary. ERROR: XST failed' My verilog code consists of following operations: 1)Calulating the adjecancy Matrix and Path Matrix.
2)Recursive Algorithm using Task (Palnitkar says that Task and Function is Synthesizable). Also let me inform u that my code is 100% behavorial. While synthesizing It shows 'Enabling Task ' for 8 hrs and then shows above error. If u know anything about the above error please tell me as the deadline is approaching fastly for project submission. Looking for ur help Thanx Saroj mail me at: XXXX@XXXXX.COM 5. Hi, Does nebody know, how to get Xilinx EDK (Embedded Design Kit)(also named as Plateform Studio) Software? Will i have to purchase from Xilinx or can i freely download that from any Xilinx link?
Eagerly waiting for ur reply. Regards, Navin 6.